Machine Learning for Defect Detection in Design-for-Testability Processes: Techniques and Trends

Sri Harsha Panchali, Usha Mohani kavirayani, Krishna Bhardwaj Mylavarapu, Jenitha Pilli, Prathik Kumar Jannu, Javed Ali Mohammad

Citation: Sri Harsha Panchali, Usha Mohani kavirayani, Krishna Bhardwaj Mylavarapu, Jenitha Pilli, Prathik Kumar Jannu, Javed Ali Mohammad, "Machine Learning for Defect Detection in Design-for-Testability Processes: Techniques and Trends", Universal Library of Engineering Technology, Special Issue.

Copyright: This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

In the current fast changing technology, accuracy, reliability and efficiency in defect detection have risen to be key to sustain the quality and performance of current semiconductor and electronic system. In this paper, the inadequacy of traditional methods of inspection in the ever-growing complexity, density, and variability of defects in modern manufacturing contexts has been reviewed as being the foundation of the approach. Combining machine learning methods with proven Design-for-Testability (DFT) methods enable organizations to discover defects much more efficiently, to eliminate testing costs, and to obtain diagnostic accuracy at a higher level. The strengths of the supervised, unsupervised and reinforcement learning methods were discussed as well as practical DFT mechanisms, including scan chains, memory BIST and serial scan architecture. Anomaly detection systems, convolutional neural networks, and autoencoders are a few examples of modern deep learning architectures that show promise for improving pattern identification and training to accommodate changing fault patterns. Regardless of these developments, there are still 4 areas that have challenges, namely, data quality, interpretability, cost of computation and resource-constrained deployment. On the whole, the review helps to realize that the combination of ML-based detection and DFT techniques opens a future direction in creating a more robust, scalable, and intelligent testing architecture that can be utilized to serve next-generation VLSI design and defect-sensitive industrial applications.


Keywords: Design-for-Testability (DFT), Machine Learning (ML), Defect Detection, VLSI Testing, Built-In Self-Test (BIST), Scan Design, Supervised Learning.

Download doi https://doi.org/10.70315/uloap.ulete.2023.008